View ADV7120KP30-REEL_1488308.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a cmos 80 mhz, triple 8-bit video dac adv7120 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram ref white pixel input port ior iog iob r0 r7 clock 8 sync adv7120 v ref gnd g0 g7 8 b0 b7 8 blank fs adjust 8 8 8 i sync v aa reference amplifier comp dac control register sync control red register green register blue register dac dac product highlights 1. fast video refresh rate, 80 mhz. 2. compatible with a wide variety of high resolution color graphics video systems. 3. guaranteed monotonic with a maximum differential non- linearity of 0.5 lsb. integral nonlinearity is guaranteed to be a maximum of 1 lsb. general description the adv7120 (adv ) is a digital to analog video converter on a single monolithic chip. the part is specifically designed for high resolution color graphics and video systems. it is also ideal for any high speed communications type applications requiring low cost, high speed dacs. it consists of three, high speed, 8-bit, video d/a converters (rgb); a standard ttl input inter- face and high impedance, analog output, current sources. the adv7120 has three separate, 8-bit, pixel input ports, one each for red, green and blue video data. additional video input controls on the part include composite sync, blank and refer- ence white. a single +5 v supply, an external 1.23 v reference and pixel clock input are all that are required to make the part operational. the adv7120 is capable of generating rgb video output sig- nals, which are compatible with rs-343a and rs-170 video standards, without requiring external buffering. the adv7120 is fabricated in a +5 v cmos process. its monolithic cmos construction ensures greater functionality with low power dissipation. the part is packaged in both a 0.6", 40-pin plastic dip and a 44-pin plastic leaded (j-lead) chip car- rier, plcc. the adv7120 is also available in a very small 48- lead thin quad flatpack (tqfp). adv is a registered trademark of analog devices, inc. *speed grades up to 140 mhz are also available upon special request. please contact analog devices or its representatives for further details. features 80 mhz pipelined operation triple 8-bit d/a converters rs-343a/rs-170 compatible outputs ttl compatible inputs +5 v cmos monolithic construction 40-pin dip or 44-pin plcc and 48-lead tqfp applications high resolution color graphics cae/cad/cam applications image processing instrumentation video signal reconstruction desktop publishing direct digital synthesis (dds) and i/q modulation speed grades* 80 mhz 50 mhz 30 mhz
rev. b C2C adv7120Cspecifications parameter all versions units test conditions/comments static performance resolution (each dac) 8 bits accuracy (each dac) integral nonlinearity, inl 1 lsb max differential nonlinearity, dnl 0.5 lsb max guaranteed monotonic gray scale error 5 % gray scale max max gray scale current: iog = (v ref * 12,082/r set ) ma ior, iob = (v ref * 8,627/r set ) ma coding binary digital inputs input high voltage, v inh 2 v min input low voltage, v inl 0.8 v max input current, i in 1 m a max v in = 0.4 v or 2.4 v input capacitance, c in 2 10 pf max analog outputs gray scale current range 15 ma min 22 ma max output current white level relative to blank 17.69 ma min typically 19.05 ma 20.40 ma max white level relative to black 16.74 ma min typically 17.62 ma 18.50 ma max black level relative to blank 0.95 ma min typically 1.44 ma 1.90 ma max blank level on ior, iob 0 m a min typically 5 m a 50 m a max blank level on iog 6.29 ma min typically 7.62 ma 9.5 ma max sync level on iog 0 m a min typically 5 m a 50 m a max lsb size 69.1 m a typ dac to dac matching 5 % max typically 2% output compliance, v oc C1 v min +1.4 v max output impedance, r out 2 100 k w typ output capacitance, c out 2 30 pf max i out = 0 ma voltage reference voltage reference range, v ref 1.14/1.26 v min/v max v ref = 1.235 v for specified performance input current, i vref C5 ma typ power requirements v aa 5 v nom i aa 125 ma max typically 80 ma: 80 mhz parts 100 ma max typically 70 ma: 50 mhz & 35 mhz parts power supply rejection ratio 0.5 %/% max typically 0.12%/%: f = 1 khz, comp = 0.1 m f power dissipation 625 mw max typically 400 mw: 80 mhz parts 500 mw max typically 350 mw: 50 mhz & 30 mhz parts dynamic performance glitch impulse 2, 3 50 pv secs typ dac noise 2, 3, 4 200 pv secs typ analog output skew 2 ns max typically 1 ns notes 1 temperature range (t min to t min ); 0 c to +70 c. 2 sample tested at +25 c to ensure compliance. 3 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. see timing notes in figure 1. 4 this includes effects due to clock and data feedthrough as well as rgb analog crosstalk. specifications subject to change without notice. (v aa = +5 v 6 5%; v ref = +1.235 v; r l = 37.5 v , c l = 10 pf; r set = 560 v . i sync connected to i0g. all specifications t min to t max 1 unless otherwise noted.)
adv7120 rev. b C3C timing characteristics 1 (v aa = +5 v 6 5%; v ref = +1.235 v; r l = 37.5 v , c l = 10 pf; r set = 560 v . i sync connected to iog. all specifications t min to t max 2 unless otherwise noted.) parameter 80 mhz version 50 mhz version 30 mhz version units conditions/comments f max 80 50 30 mhz max clock rate t l 3 6 8 ns min data & control setup time t 2 2 2 2 ns min data & control hold time t 3 12.5 20 33.3 ns min clock cycle time t 4 4 7 9 ns min clock pulse width high time t 5 4 7 9 ns min clock pulse width low time t 6 30 30 30 ns max analog output delay 20 20 20 ns typ t 7 3 3 3 ns max analog output rise/fall time t 8 3 12 15 15 ns typ analog output transition time notes 1 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. see timing notes in figure 1. 2 temperature range (t min to t max ): 0 c to +70 c 3 sample tested at +25 c to ensure compliance. specifications subject to change without notice. clock data t 2 t 4 t 5 t 8 t 7 t 6 analog outputs (ior, iog, iob, i sync ) t 3 t 1 digital inputs (r0-r7, g0-g7, b0-b7; sync, blank, ref white) notes 1. output delay ( t 6 ) measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 2. transition time ( t 8 ) measured from the 50% point of full-scale transition to within 2% of the final output value. 3. output rise/fall time ( t 7 ) measured between the 10% and 90% points of full transition. figure 1. video input/output timing
adv7120 rev. b C4C recommended operating conditions parameter symbol min typ max units power supply v aa 4.75 5.00 5.25 volts ambient operating temperature t a 0 +70 c output load r l 37.5 w reference voltage v ref 1.14 1.235 1.26 volts warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv7120 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v voltage on any digital pin . . . . . gnd C0.5 v to v aa +0.5 v ambient operating temperature (t a ) . . . . . . . . 0 c to +70 c storage temperature (t s ) . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . +150 c soldering temperature (10 secs) . . . . . . . . . . . . . . . . . . 300 c vapor phase soldering (1 minute) . . . . . . . . . . . . . . . . . 220 c ior, iob, iog, i sync to gnd 2 . . . . . . . . . . . . . . 0 v to v aa notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. ordering guide temperature package model speed range 1 option 2 adv7120kn80 80 mhz 0 c to +70 c n-40a adv7120kn50 50 mhz 0 c to +70 c n-40a adv7120kn30 30 mhz 0 c to +70 c n-40a adv7120kp80 80 mhz 0 c to +70 c p-44a adv7120kp50 50 mhz 0 c to +70 c p-44a adv7120kp30 30 mhz 0 c to +70 c p-44a adv7120kst50 50 mhz 0 c to +70 c st-48 adv7120kst30 30 mhz 0 c to +70 c st-48 notes 1 industrial temperature range (C40 c to +85 c) version available to special request. please consult your local analog device representative. 2 n = plastic dip; p = plastic leaded chip carrier. pin configurations dip g6 v aa gnd v aa gnd r4 r5 r3 r2 g0 g1 g2 fs adjust v ref comp r6 r7 r1 r0 g3 ior g4 iog g5 i sync g7 iob gnd b0 clock b1 ref white b6 b2 b7 b4 b5 13 30 1 2 40 39 5 6 7 36 35 34 3 4 38 37 833 932 10 31 11 11 12 29 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 top view (not to scale) adv7120 b3 blank sync note for the adv7120 in tqfp package: the ref white pin is not available. the i sync pin is not available and is internally connected to the iog pin. tqfp ior iog v aa iob clock v aa g0 g1 g4 g5 g6 g2 g3 r7 r6 r3 r2 r1 r5 b0 b1 b4 b5 b6 b2 b3 r4 fs adjust v ref comp nc gnd b7 r0 gnd gnd gnd gnd v aa g7 44 2 6 4 5 18 1 35 34 33 37 36 3 7 8 11 12 13 9 10 20 39 21 24 23 22 38 40 41 42 25 28 27 26 43 31 30 29 32 15 16 17 14 top view (not to scale) adv7120 blank sync 48 47 46 45 19 gnd gnd nc nc gnd nc nc = no connect plcc ior iog v aa v aa iob i sync v aa g0 g1 g4 g5 g6 g2 g3 r7 r6 r3 r2 r1 r5 b0 b1 b4 b5 b6 b2 b3 r4 fs adjust v ref comp ref white clock gnd b7 r0 gnd gnd gnd gnd v aa g7 44 1 2 6 4 5 21 24 23 22 18 20 19 39 38 35 34 33 37 36 3 7 8 11 12 13 9 10 40 41 42 25 28 27 26 43 31 30 29 32 15 16 17 14 top view (not to scale) adv7120 blank sync
adv7120 rev. b C5C pin function description pin mnemonic function blank composite blank control input (ttl compatible). a logic zero on this control input drives the analog out- puts, ior, iob and iog, to the blanking level. the blank signal is latched on the rising edge of clock. while blank is a logical zero, the r0Cr7, g0Cg7, r0Cr7 and ref white pixel and control inputs are ignored. sync composite sync control input (ttl compatible). a logical zero on the sync input switches off a 40 ire current source on the i sync output. sync does not override any other control or data input; therefore, it should only be asserted during the blanking interval. sync is latched on the rising edge of clock. clock clock input (ttl compatible). the rising edge of clock latches the r0Cr7, g0Cg7, b0Cb7, sync , blank and ref white pixel and control inputs. it is typically the pixel clock rate of the video system. clock should be driven by a dedicated ttl buffer. ref white reference white control input (ttl compatible). a logical one on this input forces the ior, iog and iob outputs to the white level, regardless of the pixel input data (r0Cr7, g0Cg7 and b0Cb7). ref white is latched on the rising edge of clock. r0Cr7, red, green and blue pixel data inputs (ttl compatible). pixel data is latched on the rising edge of clock. g0Cg7, r0, g0 and b0 are the least significant data bits. unused pixel data inputs should be connected to either the b0Cb7 regular pcb power or ground plane. ior, iog, iob red, green, and blue current outputs. these high impedance current sources are capable of directly driving a doubly terminated 75 w coaxial cable. all three current outputs should have similar output loads whether or not they are all being used. i sync sync current output. this high impedance current source can be directly connected to the iog output. this allows sync information to be encoded onto the green channel. i sync does not output any current while sync is at logical zero. the amount of current output at i sync while sync is at logical one is given by: i sync (ma) = 3,455 v ref (v)/ r set ( w ) if sync information is not required on the green channel, i sync should be connected to agnd. fs adjust full-scale adjust control. a resistor (r set ) connected between this pin and gnd, controls the magnitude of the full-scale video signal. note that the ire relationships are maintained, regardless of the full-scale output current. the relationship between r set and the full-scale output current on iog (assuming i sync is connected to iog) is given by: r set ( w ) = 12,082 v ref (v)/iog (ma) the relationship between r set and the full-scale output current on ior and iob is given by: ior, iob (ma) = 8,628 v ref (v)/ r set ( w ) comp compensation pin. this is a compensation pin for the internal reference amplifier. a 0.1 m f ceramic capaci- tor must be connected between comp and v aa . v ref voltage reference input. an external 1.2 v voltage reference must be connected to this pin. the use of an ex- ternal resistor divider network is not recommended. a 0.1 m f decoupling ceramic capacitor should be con- nected between v ref and v aa . v aa analog power supply (5 v 5%). all v aa pins on the adv7120 must be connected. gnd ground. all gnd pins must be connected.
adv7120 rev. b C6C terminology blanking level the level separating the sync portion from the video portion of the waveform. usually referred to as the front porch or back porch. at 0 ire units, it is the level which will shut off the pic- ture tube, resulting in the blackest possible picture. color video (rgb) this usually refers to the technique of combining the three pri- mary colors of red, green and blue to produce color pictures within the usual spectrum. in rgb monitors, three dacs are required, one for each color. sync signal ( sync ) the position of the composite video signal which synchronizes the scanning process. gray scale the discrete levels of video signal between reference black and reference white levels. an 8-bit dac contains 256 different lev- els while a 6-bit dac contains 64. raster scan the most basic method of sweeping a crt one line at a time to generate and display images. reference black level the maximum negative polarity amplitude of the video signal. reference white level the maximum positive polarity amplitude of the video signal. sync level the peak level of the sync signal. video signal that portion of the composite video signal which varies in gray scale levels between reference white and reference black. also referred to as the picture signal, this is the portion which may be visually observed. circuit description and operation the adv7120 contains three 8-bit d/a converters, with three input channels each containing an 8-bit register. also inte- grated on board the part is a reference amplifier and crt con- trol functions blank , sync and ref white. digital inputs 24-bits of pixel data (color information) r0Cr7, g0Cg7 and b0Cb7 are latched into the device on the rising edge of each clock cycle. this data is presented to the three 8-bit dacs and is then converted to three analog (rgb) output waveforms. (see figure 2.) three other digital control signals are latched to the analog video outputs in a similar fashion. blank , sync and ref white are each latched on the rising edge of clock to maintain synchronization with the pixel data stream. the blank and sync functions allow for the encoding of these video synchronization signals onto the rgb video output. this is done by adding appropriately weighted current sources to the analog outputs, as determined by the logic levels on the blank and sync digital inputs. figure 3 shows the analog output, rgb video waveform of the adv7120. the influence of sync and blank on the analog video waveform is illustrated. the ref white control input drives the rgb video outputs to the white level. this function could be used to overlay a cur- sor or crosshair onto the rgb video output. table i details the resultant effect on the analog outputs of blank , sync and ref white. all these digital inputs are specified to accept ttl logic levels. clock input the clock input of the adv7120 is typically the pixel clock rate of the system. it is also known as the dot rate. the dot rate, and hence the required clock frequency, will be determined by the on-screen resolution, according to the following equation: dot rate = (horiz: res) (vert res) (refresh rate)/ (retrace factor) horiz res = number of pixels/line vert res = number of lines/frame refresh rate = horizontal scan rate. this is the rate at which the screen must be refreshed, typi- cally 60 hz for a noninterlaced system or 30 hz for an interlaced system. retrace factor = total blank time factor. this takes into ac- count that the display is blanked for a cer- tain fraction of the total duration of each frame (e.g., 0.8). clock analog outputs (ior, iog, iob, i sync ) digital inputs (r0-r7, g0-g7, b0-b7; sync, blank, ref white) data figure 2. video data input/output
adv7120 rev. b C7C if we, therefore, have a graphics system with a 1024 1024 resolution, a noninterlaced 60 hz refresh rate and a retrace fac- tor of 0.8, then: dot rate = 1024 1024 60/0.8 = 78.6 mhz the required clock frequency is thus 78.6 mhz. all video data and control inputs are latched into the adv7120 on the rising edge of clock, as previously described in the digital inputs section. it is recommended that the clock input to the adv7120 be driven by a ttl buffer (e.g., 74f244). 92.5 ire 7.5 ire 40 ire white level black level blank level sync level 19.05 0.714 26.67 1.000 1.44 0.054 9.05 0.340 0 0 7.62 0.286 0 0 ma v ma v red, blue green notes 1. outputs connected to a doubly terminated 75 w load. 2. v ref = 1.235v, r set = 560 w , i sync connected to iog. 3. rs-343a levels and tolerances assumed on all levels. figure 3. rgb video output waveform video synchronization and control the adv7120 has a single composite video sync ( sync ) input control. many graphics processors and crt controllers have the ability of generating horizontal sync (hsync), vertical sync (vsync) and composite sync . in a graphics system which does not automatically generate a composite sync signal, the inclusion of some additional logic circuitry will enable the generation of a composite sync signal. the i sync current output is typically connected directly to the iog output, thus encoding video synchronization information onto the green video channel. if it is not required to encode sync information onto the adv7120s analog outputs, the sync in- put should be tied to logic low and the i sync should be con- nected to analog ground. reference input an external 1.23 v voltage reference is required to drive the adv7120. the ad589 from analog devices is an ideal choice of reference. it is a two-terminal, low cost, temperature compensated bandgap voltage reference which provides a fixed 1.23 v output voltage for input currents between 50 m a and 5 ma. figure 4 shows a typical refer- ence circuit connection diagram. the voltage reference gets its current drive from the adv7120s v aa through an on- board 1 k w resistor to the v ref pin. a 0.1 m f ceramic ca- pacitor is required between the comp pin and v aa . this is necessary so as to provide compensation for the internal reference amplifier. table i. video output truth table iog ior, iob ref dac description (ma) l (ma) white sync blank input data white level 26.67 19.05 1 1 1 xxh white level 26.67 19.05 0 1 1 ffh video video + 9.05 video + 1.44 0 1 1 data video to blank video + 1.44 video + 1.44 0 0 1 data black level 9.05 1.44 0 1 1 00h black to blank 1.44 1.44 0 0 1 00h blank level 7.62 0 0 1 0 xxh sync level 0 0 0 0 0 xxh note typical with full-scale iog = 26.67 ma. v ref = 1.235 v, r set = 560 w , i sync connected to iog.
adv7120 rev. b C8C a resistance r set connected between fs adjust and gnd determines the amplitude of the output video level according to the following equations: iog (ma) = 12,082 v ref (v)/r set ( w ) (1) ior, iob (ma) = 8,628 v ref (v)/r set ( w ) (2) if sync is not being encoded onto the green channel, then equation 1 will be similar to equation 2. using a variable value of r set , as shown in figure 4, allows for accurate adjustment of the analog output video levels. use of a fixed 560 w r set resistor yields the analog output levels as quoted in the specification page. these values also correspond to the rs-343a video waveform values as shown in figure 3. to dacs adv7120* v aa v ref gnd 1k w fs adjust r set 560 w 500 w 100 w *additional circuitry, including decoupling components, excluded for clarity analog power plane comp 0.1 m f 5v + ad589 (1.235v voltage reference) i ref ? 4ma figure 4. reference circuit d/a converters the adv7120 contains three matched 8-bit d/a converters. the dacs are designed using an advanced, high speed, seg- mented architecture. the bit currents corresponding to each digital input are routed to either the analog output (bit = 1) or gnd (bit = 0) by a sophisticated decoding scheme. as all this circuitry is on one monolithic device, matching between the three dacs is optimized. as well as matching, the use of identi- cal current sources in a monolithic design guarantees monoto- nicity and low glitch. the onboard operational amplifier stabilizes the full-scale output current against temperature and power supply variations. analog outputs the adv7120 has three analog outputs, corresponding to the red, green and blue video signals. a fourth analog output (i sync ) can be used if it is required to encode video synchronization inf ormation onto the green signal. in this case, i sync is connected to iog . (see video synchronization and control section.) the red, green and blue analog outputs of the adv7102 are high impedance current sources. each one of these three rgb current outputs is capable of directly driving a 37.5 w load, such as a doubly terminated 75 w coaxial cable. figure 5a shows the required configuration for each of the three rgb outputs con- nected into a doubly terminated 75 w load. this arrangement will develop rs-343a video output voltage levels across a 75 w monitor. termination repeated three times for red, green and blue dacs dacs ior, iog, iob (cable) z o = 75 w z s = 75 w (source termination) z l = 75 w (monitor) figure 5a. analog output termination for rs-343a one suggested method of driving rs-170 video levels into a 75 w monitor is shown in figure 5b. the output current levels of the dacs remain unchanged but the source termination resistance, z s , on each of the three dacs is increased from 75 w to 150 w . termination repeated three times for red, green and blue dacs dacs ior, iog, iob (cable) z o = 75 w z s = 150 w (source termination) z l = 75 w (monitor) figure 5b. analog output termination for rs-170 more detailed information regarding load terminations for vari- ous output configurations, including rs-343a and rs-170, is available in an application note entitled video formats & re- quired load terminations available from analog devices, publication number e1228-15-1/89. figure 3 shows the video waveforms associated with the three rgb outputs driving the doubly terminated 75 w load of figure 5a. as well as the gray scale levels, black level to white level, the diagram also shows the contributions of sync and blank . these control inputs add appropriately weighted currents to the analog outputs, producing the specific output level requirements for video applications. table i details how the sync and blank inputs modify the output levels. gray scale operation the adv7120 can be used for stand-alone, gray scale (mono- chrome) or composite video applications (i.e., only one channel used for video information). any one of the three channels, red, green or blue, can be used to input the digital video data. the two unused video data channels should be tied to logical zero.
adv7120 rev. b C9C the unused analog outputs should be terminated with the same load as that for the used channel. in other words, if the red channel is used and ior is terminated with a doubly terminated 75 w load (37.5 w ), iob and iog should be terminated with 37.5 w resistors. (see figure 6.) gnd adv7120 r0 r7 g0 g7 b0 b7 video input doubly terminated 75 w load ior iog iob 37.5 w 37.5 w figure 6. input and output connections for stand-alone gray scale or composite video video output buffers the adv7120 is specified to drive transmission line loads, which is what most monitors are rated as. the analog output configurations to drive such loads are described in the analog interface section and illustrated in figure 5. however, in some applications it may be required to drive long transmission line cable lengths. cable lengths greater than 10 meters can attenu- ate and distort high frequency analog output pulses. the inclu- sion of output buffers will compensate for some cable distortion. buffers with large full power bandwidths and gains between 2 and 4 will be required. these buffers will also need to be able to supply sufficient cur- rent over the complete output voltage swing. analog devices produces a range of suitable op amps for such applications. these include the ad84x series of monolithic op amps. in very high frequency applications (80 mhz), the ad9617 is recom- mended. more information on line driver buffering circuits is given in the relevant op amp data sheets. use of buffer amplifiers also allows implementation of other video standards besides rs-343a and rs-170. altering the gain components of the buffer circuit will result in any desired video level. 7 6 4 3 2 ad848 dacs ior, iog, iob (cable) z o = 75 w z s = 75 w (source termination) z l = 75 w (monitor) 0.1 m f 75 w +v s z 1 z 2 ? s 0.1 m f gain (g) = 1 + z 1 z 2 figure 7. ad848 as an output buffer
adv7120 rev. b C10C pc board layout considerations the adv7120 is optimally designed for lowest noise perfor- mance, both radiated and conducted noise. to complement the excellent noise performance of the adv7120, it is imperative that great care be given to the pc board layout. figure 8 shows a recommended connection diagram for the adv7120. the layout should be optimized for lowest noise on the adv7120 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should by minimized so as to minimize inductive ringing. ground planes the adv7120 and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. this ground plane should connect to the regular pcb ground plane at a single point through a ferrite bead, as illustrated in figure 8. this bead should be located as close as possible (within 3 inches) to the adv7120. the analog ground plane should encompass all adv7120 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces and any output amplifiers. the regular pcb ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the adv7120. gnd fs adjust ior iog iob ground adv7120 c3 0.1 m f c5 0.1 m f z1 (ad589) r1 75 w r2 75 w r3 75 w c1 33 m f c2 10 m f comp c6 0.1 m f analog power plane v aa v ref l2 (ferrite bead) r0 r7 g0 g7 b0 b7 clock ref white sync blank rgb video output video data inputs video control inputs analog ground plane c4 0.1 m f r set 560 w l1 (ferrite bead) +5v (v cc ) i sync set component c1 c2 c3, c4, c5, c6 l1, l2 r1, r2, r3 rset z1 set description 33 m f tantalum capacitor 10 m f tantalum capacitor 0.1 m f ceramic capacitor ferrite bead 75 w 1% metal film resistor 560 w 1% metal film resistor 1.235v voltage reference vendor part number fair-rite 274300111 or murata bl01/02/03 dale cmf-55c dale cmf-55c analog devices ad589jh figure 8. adv7120 typical connection diagram and component list
adv7120 rev. b C11C power planes the pc board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. the analog power plane should encompass the adv7120 (v aa ) and all as- sociated analog circuitry. this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead, as illustrated in figure 8. this bead should be lo- cated within three inches of the adv7120. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7120 power pins, voltage reference circuitry and any output amplifiers. the pcb power and ground planes should not overlay portions of the analog power plane. keeping the pcb power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. supply decoupling noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors. (see figure 8.) optimum performance is achieved by the use of 0.1 m f ceramic capacitors. each of the two groups of v aa should be individually decoupled to ground. this should be done by placing the ca- pacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. it is important to note that while the adv7120 contains cir- cuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reducing power sup- ply noise. a dc power supply filter (murata bnx002) will pro- vide emi suppression between the switching power supply and the main pcb. alternatively, consideration could be given to using a three terminal voltage regulator. digital signal interconnect the digital signal lines to the adv7120 should be isolated as much as possible from the analog outputs and other analog cir- cuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the adv7120 should be avoided so as to minimize noise pickup. any active pull-up termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ), and not the analog power plane. analog signal interconnect the adv7120 should be located as close as possible to the out- put connectors thus minimizing noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high fre- quency power supply rejection. for optimum performance, the analog outputs should each have a source termination resistance to ground of 75 w (doubly ter- minated 75 w configuration). this termination resistance should be as close as possible to the adv7120 so as to minimize reflections. additional information on pcb design is available in an applica- tion note entitled design and layout of a video graphics sys- tem for reduced emi. this application note is available from analog devices, publication number e1309-15-10/89.
adv7120 rev. b C12C outline dimensions dimensions shown in inches and (mm). c1379C24C4/90 printed in u.s.a. 44-terminal plastic leaded chip carrier (p-44a) 6 pin 1 identifier 7 40 39 17 18 29 28 top view (pins down) 0.695 (17.65) 0.685 (17.40) sq 0.656 (16.662) 0.650 (16.510) sq 0.045 typ 0.045 typ r.020 max 3 plcs 0.021 (0.533) 0.013 (0.331) 0.630 (16.00) 0.590 (14.99) 0.032 (0.812) 0.026 (0.661) 0.180 (4.57) 0.165 (4.20) 0.120 (3.04) 0.090 (2.29) 0.045 typ 0.045 typ 0.020 min 0.050 0.005 (1.27 0.13) 40-pin plastic dip (n-40a) 0.17 (4.32) max 0.021 (0.533) 0.015 (0.381) 0.175 (4.45) 0.125 (3.18) 1 40 0.545 (13.843) 0.535 (13.589) 20 21 0.052 (1.32) 0.048 (1.219) 0.630 (16.0) 0.590 (15.0) 0.012 (0.305) 0.008 (0.203) 15 0 2.090 (53.0) 2.008 (51.0) 0.155 (3.937) 0.145 (3.683) 0.105 (2.67) 0.095 (2.42) lead no. 1 identified by dot, notch or "1." leads are solder plated kovar or alloy 42. 48-lead tqfp (st-48) 0.354 0.008 (9.00 0.2) 0.276 0.004 (7.0 0.1) 0.02 0.003 (0.50 0.08) 0.007 0.003 ?.001 (0.18 0.08 ?.03) 0.276 0.004 (7.0 0.1) 0.354 0.008 (9.00 0.2) 1 12 13 25 24 36 37 48 top view (pins down) seating plane 0.055 0.002 (1.40 0.05) 0.02 0.008 (0.5 0.02) 0 min 0.059 +0.008 ?.004 (1.50 +0.2 ?.1) 0.005 +0.002 ?.0008 (0.127 +0.05 ?.02) 0.004 0.002 (0.1 0.05) (3.5 3.5 )

▲Up To Search▲

Price & Availability of ADV7120KP30-REEL

	To Download ADV7120KP30-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .